ARITHMETIC SYSTEM FOR INFORMATION PROCESSOR

• Main Authors: OKADA TETSUHIKO, MATSUI SHIGEZUMI
• Format: Patent
• Language: English
• Published: 16.05.1988
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE:To increase the arithmetic processing speed by connecting switches to each signal line consisting of a precharge type bus to decide the discharge in response to the arithmetic data and the mask data. CONSTITUTION:In the executing unit of a microcomputer, the buses BUS 1 and 2 connected with an arithmetic and logic unit ALU are constituted of precharge system buses. A data register REG 11 and the mask register REG 12 are connected to the BUS 1 via switches S11 and S12, while second registers REG 21 and 22 are connected to the BUS 2 via switches S21 and 22 respectively. When the arithmetic data on the REG 11, for example, is put on the BUS 1, the S12 is turned on to put the mask data on the REG 12 on the BUS 1. Then the charge on a signal line corresponding to logic 0 of the mask data is discharged and supplied to the ALU.