SEMICONDUCTOR SUBSTRATE HOUSING

• Main Author: KUMAGAI SEIICHI
• Format: Patent
• Language: English
• Published: 27.08.1987
• Subjects: ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; BASIC ELECTRIC ELEMENTS; CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; CONVEYING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; HANDLING THIN OR FILAMENTARY MATERIAL; PACKAGES; PACKAGING ELEMENTS; PACKING; PERFORMING OPERATIONS; SEMICONDUCTOR DEVICES; STORING; TRANSPORTING

PURPOSE:To make difficult to come into contact the surfaces of semiconductor substrates to the guide plates and the supporting parts of the titled housing box at the time of insertion of the semiconductor substrates and when the semiconductor substrates are held by a method wherein the guide plates for inserting the semiconductor substrates and the supporting parts for holding the semiconductor substrates are slanted in the extent of not damaging the basic efficiency of holding the substrates in the vertical direction to the installing surface of the semiconductor substrate housing box. CONSTITUTION:Each semiconductor substrate 3 is inserted from a semiconductor substrate guide plate 1 slanted at an angle (theta) from the vertical direction to the installing surface of a semiconductor substrate housing box in such a way as not to come into contact with the guide plate 1 facing a surface 3-a and a back surface 3-b, which form a semiconductor device, upward and downward respectively as the upper surface and the lower surface and the semiconductor substrate 3 is held by a semiconductor substrate supporting part 2 making the angle (theta) like the above. By letting the guide plate 1 and the supporting part 2 of the semiconductor substrate housing box hold the gradient, the surface of the semiconductor substrate forming the semiconductor device can be avoided from coming into contact to the guide plate 1 and the supporting part 2 at the time of insertion of the semiconductor substrate and when the semiconductor substrate is held.