MEMORY COPY SYSTEM

PURPOSE:To attain high speed copy by writing data other than all '0' to a copy destination memory with a data not all '0' and address information via a central processing unit managing the execution of copy. CONSTITUTION:When the central controller 1 sends a CLR signal to the mem...

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Bibliographic Details
Main Author TANABE YOSHIICHI
Format Patent
LanguageEnglish
Published 17.11.1986
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To attain high speed copy by writing data other than all '0' to a copy destination memory with a data not all '0' and address information via a central processing unit managing the execution of copy. CONSTITUTION:When the central controller 1 sends a CLR signal to the memory 3 being copy destination, a memory clear circuit 33 clears all areas into zero. Then the controller 1 sends a COPY signal to a memory 2 being a copy sender, a control circuit 22 of the memory 2 receives the COPY signal, then extracts a data sequentially from an address zero and sends the address information and the data to the controller 1. In this case, the result of discrimination of all zero discrimination bit arranged corresponding to each address is received from a discrimination circuit 21, and in case of all zero discrimination, the address is incremented by one to repeat the extraction of the data in the next address. In the case of other than all zero, the address information and the data are sent to the controller 1. The controller 1 sends them to the memory 3 as they are and a memory section 30 sets the data sent from the address zero to the address sent from the controller 1.
Bibliography:Application Number: JP19850100950