PULSE WIDTH MODULATOR - SASAKI MIKIO; NURIYA KOZO; SOBASHIMA AKIRA (1986)
PURPOSE:To improve the S/N by loading an n-bit data to two counters operated at a clock frequency fC at a prescribed sampling period. CONSTITUTION:A high-order (n-1)-bit of an n-bit data from an input terminal 1 is loaded to a counter 5 by using a pulse outputted from a pulse generator 3 at each sampling period TS=1/fS and the n-bit is loaded to a counter 4. After data load, the 1st counter 5 starts counting in a clock frequency fC and when the count reaches a prescribed value, the count of the 2nd counter 4 is started. When the count reaches a prescribed value, the count is stopped. Then an output of both the counters is given to a combination circuit 6, from which a signal subject to pulse width modulation is obtained. Thus, the data word length (n) to be handled is expressed as log2(fC/fS)-bit, and since the pulse width control is attained by the accuracy of the operating frequency fC, the S/N is improved.