TEST COVERAGE SYSTEM FOR LOGICAL SIMULATION

• Main Authors: WAKAI KATSURO, FUKUOKA KOHEI, KATO ZENTARO, KUBO KANJI, KONDO KUNIAKI, NAKAGAWA KOICHI
• Format: Patent
• Language: English
• Published: 14.06.1986
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PURPOSE:To improve the efficiency of logical simulation by replacing the working frequency of a specific memory means and the passing frequency through said memory means based on the signal changing information for each signal identification name of a logical circuit and the passing information for each bus identification between steps. CONSTITUTION:A coverage check information file 8 is produced with a microprogram source code file 5 and a signal information file 6 and by a coverage check information production processing 1. The file 8 contains a file which stores a correspondence table between the signal identification names of a logical circuit and the working frequencies of these names and a file which stores a correspondence table between the inter-bus identifications of a microprogram and their passing frequencies. Then a trace information file 9 is produced from a file 7, i.e., the result of a logical simulation 12 through a simulation result information analysis processing 2. Both files 8 and 9 are collated with each other through an information replacement processing 3, and the file 8 is replacement.