SIMULATION OF LOGICAL CIRCUIT

• Main Authors: KAZAMA YOSHIHARU, TADA OSAMU, MIYOSHI MASAYUKI, NAGURA YASUO
• Format: Patent
• Language: English
• Published: 09.06.1986
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

PURPOSE:To reduce the memory area, by discribing a Boolean expression using logical expression in the form of having variables connected with single operators and other single operators connecting the logical expressions to express signal values of variables belonging to one logical expression in package. CONSTITUTION:A Boolean expression is converted into a half-divided tree and low- order operators or elements to be computed connected direct to high-order operators are arranged to be nodes. The Boolean function code is determined by the high-and low-order operators to obtain the memory area value for the storage of signal values at various items from the number of elements to be computed at a low order in the nodes. The item assigning code is determined corresponding to each node to determine the byte at which the signal values of the elements to be computed contained in each node shall be stored in the signal value storage area from the area value determined. Then, the position at which the elements to be computed take/within the signal value storage area is determined. The above-mentioned processing is repeated until all nodes are covered. This eliminates the need for having a Boolean type Polish notation on a general-purpose computer in expressing logic described by the Boolean expression thereby reducing the required memory.