VERTICAL SYNCHRONIZING CIRCUIT

• Main Author: FUJIMORI TOSHIMITSU
• Format: Patent
• Language: English
• Published: 08.06.1984
• Subjects: ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PICTORIAL COMMUNICATION, e.g. TELEVISION

PURPOSE:To attain stable vertical deflection under a weak electric field condition by limiting a period when a receiving vertical synchronizing signal is impressed to a phase detecting circuit to eliminate the disturbance in the vertical deflection due to noise. CONSTITUTION:An output of a synchronizing separation circuit 1 of a TV receiver is integrated by an integration circuit 12, amplified at an amplifer 13, and applied to a gate circuit 42 while changing the polarity at an inverter 29. The polarity of the vertical synchronizing signal frequency-divided at a frequency divider 9 is changed by an inverter 30, and a waveform (a) is applied to an NOR circuit of a phase detecting circuit. A gate circuit 42 inputting an output waveform (h) of the inverter 29 is provided with a switching transistor TR 41 controlled by an output of an oscillator 40, the waveform (h) is gated by an output waveform (i) of the oscillator 40 and applied to the NOR circuit. In receiving a radio of a weak electric field, a switch 43 is turned off, the input to a phase synchronism circuit is limited to about 50msec by the gate circuit 42, the disturbance of the vertical deflection due to noise is prevented and the vertical deflection is made stable.