HIGHLY RELIABLE LOGICAL CIRCUIT

PURPOSE:To allow relief instantly by detecting oscillation failure of a logical circuit, by connecting a counter circuit provided with a reset function and an overflow detecting function to a feedback line of the logical circuit. CONSTITUTION:If an output signal 3 of a latch circuit consisting of NA...

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Bibliographic Details
Main Authors TAKAHASHI MASANOBU, FUNATSU SHIGEHIRO
Format Patent
LanguageEnglish
Published 19.05.1982
Subjects
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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Summary:PURPOSE:To allow relief instantly by detecting oscillation failure of a logical circuit, by connecting a counter circuit provided with a reset function and an overflow detecting function to a feedback line of the logical circuit. CONSTITUTION:If an output signal 3 of a latch circuit consisting of NAND gates 11, 12 is in oscillating state due to failure, since the output signal 3 is applied to a binary counter 14 of n bits as a trigger signal, the content of the binary counter 14 is summed by one at every period of oscillation. When the binary counter 14 overflows, the production of the overflow state is reported with an output signal 8 and the production of oscillation to the latch circuit is known. The binary counter 14 clears the content of counter at an arbitrary point of time with a reset signal 7.
Bibliography:Application Number: JP19800155003