INFORMATION PROCESSOR

PROBLEM TO BE SOLVED: To obtain a bus system for information processor which maximizes the use efficiency of each of three kinds of busses, namely, a system bus, a memory bus, and a processor bus. SOLUTION: The processor bus 111, to which processors 1 to N (101) are connected, the memory bus 112, to...

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Bibliographic Details
Main Authors MOCHIDA TETSUYA, KAWAGUCHI HITOSHI, KOBAYASHI ICHIJI, KIMURA KOICHI, OKAZAWA KOICHI, YUNO KAZUHARU
Format Patent
LanguageEnglish
Published 30.11.1999
Edition6
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To obtain a bus system for information processor which maximizes the use efficiency of each of three kinds of busses, namely, a system bus, a memory bus, and a processor bus. SOLUTION: The processor bus 111, to which processors 1 to N (101) are connected, the memory bus 112, to which a main memory 104 is connected, and the system bus 113, to which a connected device 105 is connected, are connected to a three-forked connection controller 103. This controller 103 performs such control that data may be mutually transferred among the processor bus 111, the memory bus 112, and the system bus 113.
Bibliography:Application Number: JP19990008828