BUS CONTROLLER AND INFORMATION PROCESSOR
PROBLEM TO BE SOLVED: To avoid the generation of a wasteful cycle for waiting synchronization with respect to an external clock signal. SOLUTION: A bus controller 3 controls access to buses 123 and 124 connected with an external device 21 operating by synchronizing with the external clock signal 100...
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Main Author | |
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Format | Patent |
Language | English |
Published |
12.12.1997
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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