NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device corresponding to a fine process by using a low-stem difference double-layer polysilicon structure. SOLUTION: The semiconductor memory device has two channel regions L1 and L2 between a source region 2 and a drain region 3. Th...

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Main Authors TANAKA MAKOTO, ITSUSHIKI KAIHEI, YAMAGUCHI KIYOSHI, KUSUNOKI MASAMUNE, ABE SHUYA, MORI KOJI, JIKUTANI NAOTO
Format Patent
LanguageEnglish
Published 02.12.1997
Edition6
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Abstract PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device corresponding to a fine process by using a low-stem difference double-layer polysilicon structure. SOLUTION: The semiconductor memory device has two channel regions L1 and L2 between a source region 2 and a drain region 3. The channel region L1 on the drain region side is formed under a floating gate electrode 24 via a gate insulating film 23, and the channel region L2 on the source region side is formed under a control gate electrode 30 via the gate insulating film 23. The control gate 30 is provided on the floating gate 24 via an insulating film 31, and further, the control gate 30 is formed in line in a channel length direction of the two channel regions. The source region 2 and the drain region 3 are arranged in line in a channel width direction such that these regions are owned in common by a plurality of semiconductor memory devices. Further, the source region 2 and the drain region 3 are alternately arranged in the channel length direction such that these regions are owned in common by adjacent semiconductor memory devices.
AbstractList PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device corresponding to a fine process by using a low-stem difference double-layer polysilicon structure. SOLUTION: The semiconductor memory device has two channel regions L1 and L2 between a source region 2 and a drain region 3. The channel region L1 on the drain region side is formed under a floating gate electrode 24 via a gate insulating film 23, and the channel region L2 on the source region side is formed under a control gate electrode 30 via the gate insulating film 23. The control gate 30 is provided on the floating gate 24 via an insulating film 31, and further, the control gate 30 is formed in line in a channel length direction of the two channel regions. The source region 2 and the drain region 3 are arranged in line in a channel width direction such that these regions are owned in common by a plurality of semiconductor memory devices. Further, the source region 2 and the drain region 3 are alternately arranged in the channel length direction such that these regions are owned in common by adjacent semiconductor memory devices.
Author MORI KOJI
ABE SHUYA
TANAKA MAKOTO
KUSUNOKI MASAMUNE
ITSUSHIKI KAIHEI
JIKUTANI NAOTO
YAMAGUCHI KIYOSHI
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– fullname: MORI KOJI
– fullname: JIKUTANI NAOTO
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Snippet PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device corresponding to a fine process by using a low-stem difference double-layer...
SourceID epo
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SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
Title NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURE THEREOF
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