SEMICONDUCTOR MEMORY

PURPOSE:To make desired ROM data latent for each memory by providing differences between resistance values of each high resistance load of a pair of inverter of a memory cell of a SRAM. CONSTITUTION:An inverter is constituted of high resistance loads 5, 6 and transistors 7, 8. And storage nodes m1,...

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Bibliographic Details
Main Author KIMURA KIKUO
Format Patent
LanguageEnglish
Published 19.05.1995
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To make desired ROM data latent for each memory by providing differences between resistance values of each high resistance load of a pair of inverter of a memory cell of a SRAM. CONSTITUTION:An inverter is constituted of high resistance loads 5, 6 and transistors 7, 8. And storage nodes m1, m2 are connected to gate terminals of transistors 8, 7 respectively, a pair of inverter is cross-coupled and formed as a flip flop to constitute a memory cell. This memory cell makes a resistance value of one side of high resistance loads 5 or 6 larger or smaller than a normal value based on contents of ROM data desired to be latent within a range of normal operation as a SRAM. Then, the flip flop may have two stable points in order to operate normally as the SRAM. Therefore, for example, when the load 5 has a high resistance value higher than the limit point having only one stable point, it has two stable points, and one bit data of a high or low level can be held as the SRAM.
Bibliography:Application Number: JP19930276702