ZOOM PROCESSING INTERPOLATION CIRCUIT FOR DIGITAL IMAGE

• Main Authors: FURUKAWA SATOSHI, YABUTA AKIRA, KITADOU MASAHARU, KURODA MINORU, TOOMASU BOGUSUTOROMU, ITO HISAHARU, MASUDA TATSUO, AOYAMA KEIICHI, HAGIO KENICHI
• Format: Patent
• Language: English
• Published: 10.02.1994
• Edition: 5
• Subjects: ADVERTISING; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION; CRYPTOGRAPHY; DISPLAY; EDUCATION; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; PHYSICS; PICTORIAL COMMUNICATION, e.g. TELEVISION; SEALS

PURPOSE:To provide the zoom processing interpolation circuit for digital image which can enlarge an original image double without degrading picture quality. CONSTITUTION:Concerning the even-number line of an image to be enlarged double, pixel data successively read from an image memory 4 are stored in a register R0 and corresponding to the storage into the register R0, the pixel data are stored in a register R1 while being delayed for one cycle. The values of these registers R0 and R1 are averaged by an adder AD1 and outputted at each time when the value stored in the register R1 is changed. Concerning the odd-number line, the pixel data successively read from the image memory 4 are stored in the register R0 and a third register R2, and the pixel data successively read from a line buffer 3 are stored in 2nd and 4th registers R3 and R4. The value of the adder AD1, the value of an adder AD2 for averaging the values of the registers R2 and R3 and the value of an adder AD3 for averaging the values of both of adders AD1 and AD2 are outputted in a prescribed order.