PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY
PURPOSE:To realize a multilevel memory by reading a memory cell when the memory cell is programmed, comparing the data with an input data and continu ing a programming operation until the write state of the memory cell is matched with the input data. CONSTITUTION:When a program control signal is mad...
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Format | Patent |
Language | English |
Published |
25.02.1992
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Abstract | PURPOSE:To realize a multilevel memory by reading a memory cell when the memory cell is programmed, comparing the data with an input data and continu ing a programming operation until the write state of the memory cell is matched with the input data. CONSTITUTION:When a program control signal is made L, a program pulse PHIpgm is outputted from a pulse generating circuit 38. With this program pulse PHIpgm, a program pulse PHIp is outputted from an AND circuit 40. According to the level of the pulse PHIp, a power supply voltage Vpp and a power supply voltage Vcc are alternately outputted from a switching circuit 20. The Vpp is impressed to a Y gate 24 of a word line 160 to be designated by an address to be impressed from the outside. According to the input data impressed from the outside, an inverter 30 supplies a high voltage approximate to the Vpp or a GND potential through a NOR circuit 37 and a NAND circuit 36 to a bit line 22. Then, the input data is written. |
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AbstractList | PURPOSE:To realize a multilevel memory by reading a memory cell when the memory cell is programmed, comparing the data with an input data and continu ing a programming operation until the write state of the memory cell is matched with the input data. CONSTITUTION:When a program control signal is made L, a program pulse PHIpgm is outputted from a pulse generating circuit 38. With this program pulse PHIpgm, a program pulse PHIp is outputted from an AND circuit 40. According to the level of the pulse PHIp, a power supply voltage Vpp and a power supply voltage Vcc are alternately outputted from a switching circuit 20. The Vpp is impressed to a Y gate 24 of a word line 160 to be designated by an address to be impressed from the outside. According to the input data impressed from the outside, an inverter 30 supplies a high voltage approximate to the Vpp or a GND potential through a NOR circuit 37 and a NAND circuit 36 to a bit line 22. Then, the input data is written. |
Author | OKUBO HIDE |
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Notes | Application Number: JP19900164849 |
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PublicationDate | 19920225 |
PublicationDateYYYYMMDD | 1992-02-25 |
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PublicationYear | 1992 |
RelatedCompanies | RICOH CO LTD |
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Snippet | PURPOSE:To realize a multilevel memory by reading a memory cell when the memory cell is programmed, comparing the data with an input data and continu ing a... |
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SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY INFORMATION STORAGE PHYSICS SEMICONDUCTOR DEVICES STATIC STORES |
Title | PROGRAMMABLE NON-VOLATILE SEMICONDUCTOR MEMORY |
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