PSEUDO RANDOM PATTERN COMPARATOR CIRCUIT - MATSUDA TAKAO (1991)
PURPOSE:To shorten the test time without increasing the circuit scale by providing a memory having one memory space per channel, an s-adic counter, a PN pattern generating section and a comparator and comparing all channels simultaneously. CONSTITUTION:A data sectioned in p-bit per channel is subject to time division multiplex by s-channel and the time division multiplex data is subject to serial/ parallel conversion and the result is inputted to a comparator 14 and a selector 15 respectively in p-bit parallel. A memory 11 has n-bit input and output terminals respectively and uses s-set of memory spaces. Since the time division multiplex data is processed in parallel and the PN pattern comparison result of all channels in one frame is stored in the memory 11 in this way, the presence of a data error in all channels is monitored by a time having been required for the monitor of the presence of the data error in one channel in a conventional circuit and the test time is shortened to one over channel numbers and the circuit scale is made small.