DEBUG MECHANISM FOR PROCESSOR

PURPOSE:To realize the individual debugging jobs for the host and guest programs by preparing a mode to prescribe the host and guest programs to be debugged and validating the program debugging function in accordance with the mode. CONSTITUTION:A guest debugging mode is set via a control panel 16, a...

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Bibliographic Details
Main Author WAKUI FUJIO
Format Patent
LanguageEnglish
Published 23.03.1990
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PURPOSE:To realize the individual debugging jobs for the host and guest programs by preparing a mode to prescribe the host and guest programs to be debugged and validating the program debugging function in accordance with the mode. CONSTITUTION:A guest debugging mode is set via a control panel 16, and a guest program is started by a host program. Thus a muP execution control part 3 decides a guest identification mode 12 and sets a guest execution mode 11 to execute successively the instructions. Then a comparison coincidence detecting circuit 14 produces a CPU stop trigger 15 to be given to the part 3 when the circuit 14 executes an instruction coincident with a prescribed address. Thus the working of the CPU is stopped. While the host program is also debugged in the same way when a host debugging mode is set via the panel 16. The mode 11 is reset in the case a program discordant with the set mode is carried out. Thus the trigger 15 is not produced. In such a way, both host and guest programs can be debugged.
Bibliography:Application Number: JP19880235061