PROCESSING EQUIPMENT

• Main Author: TATEYAMA MASAYOSHI
• Format: Patent
• Language: English
• Published: 01.11.1990
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PURPOSE:To prevent mark arrangement error and dicing line preparation error by a method wherein, based on input data concerning a chip, the following are preformed; computations of position coordinates of mask alignment mark and mark periphery coordinates, mark data arrangement, and preparation of dicing lines. CONSTITUTION:According to arrangement rule and dicing line preparation rule data previously registered based on input chip size value, position coordinates of mask alignment mark and mark periphery coordinates are computed. Mark data arrangement is performed based on the computed position coordinates of mask alignment mark and data previously registered in a mark cell library. Dicing lines are prepared from computed mark periphery coordinates and dicing line preparing rule data. As a result, based on an operator's input data with regard to a chip, the following are performed; computation of arrangement position of mask alignment mark, arrangement of mask alignment marks, and formation of layout data necessary to prepare dicing lines in a region where marks are not arranged. Thereby arrangement error and dicing line preparation error can be prevented.