JP2992992B
PURPOSE:To simplify a signal processing in a decoding system, and to transmit picture information through less transmission quantity by selecting optionally plural ways of coding by considering a dynamic range, and making the code length of a transmission unit constant. CONSTITUTION:An NTSC televisi...
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Main Authors | , , , , |
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Format | Patent |
Language | English |
Published |
20.12.1999
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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Abstract | PURPOSE:To simplify a signal processing in a decoding system, and to transmit picture information through less transmission quantity by selecting optionally plural ways of coding by considering a dynamic range, and making the code length of a transmission unit constant. CONSTITUTION:An NTSC television signal is inputted to a blocking circuit 12 through an A/D conversion circuit 11. A sample train divided into blocks and rearranged by the blocking circuit 12 is impressed to a minimum value detector 14, a maximum value detector 16, an intra-block mean value calculation circuit 18 and a delay circuit 20. The outputs of those are inputted to a conversion circuit 32, the conversion circuits 36, 38 and a data train generation circuit 44 through a subtracter 22 and the delay circuits 24, 26, 28, 30, etc. A selection circuit 42 selects the output of either of the delay circuit 24 or a parallel/serial conversion circuit 40. The index of each picture element is outputted from the conversion circuit 32, and the encoded data train of fixed length is outputted from the data train generation circuit 44. |
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AbstractList | PURPOSE:To simplify a signal processing in a decoding system, and to transmit picture information through less transmission quantity by selecting optionally plural ways of coding by considering a dynamic range, and making the code length of a transmission unit constant. CONSTITUTION:An NTSC television signal is inputted to a blocking circuit 12 through an A/D conversion circuit 11. A sample train divided into blocks and rearranged by the blocking circuit 12 is impressed to a minimum value detector 14, a maximum value detector 16, an intra-block mean value calculation circuit 18 and a delay circuit 20. The outputs of those are inputted to a conversion circuit 32, the conversion circuits 36, 38 and a data train generation circuit 44 through a subtracter 22 and the delay circuits 24, 26, 28, 30, etc. A selection circuit 42 selects the output of either of the delay circuit 24 or a parallel/serial conversion circuit 40. The index of each picture element is outputted from the conversion circuit 32, and the encoded data train of fixed length is outputted from the data train generation circuit 44. |
Author | SASAYA TOMOHIKO ISHII YOSHISUE FUJII AKIO SHIMOKOORYAMA MAKOTO SHIMIZU TETSUYA |
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Notes | Application Number: JP19870297410 |
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Snippet | PURPOSE:To simplify a signal processing in a decoding system, and to transmit picture information through less transmission quantity by selecting optionally... |
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SubjectTerms | BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC COMMUNICATION TECHNIQUE ELECTRICITY IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS PICTORIAL COMMUNICATION, e.g. TELEVISION TRANSMISSION |
Title | JP2992992B |
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