JP2573657B

PURPOSE:To make reading speed high by providing a Y selector for column line discharging consisting of plural MOS-FETs connected between a column line and one voltage supplying terminal and in which a signal inverting the output of a Y decoder is impressed on a gate. CONSTITUTION:To a ROM involving...

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Bibliographic Details
Main Author OBATA HIROYUKI
Format Patent
LanguageEnglish
Published 22.01.1997
Edition6
Subjects
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PURPOSE:To make reading speed high by providing a Y selector for column line discharging consisting of plural MOS-FETs connected between a column line and one voltage supplying terminal and in which a signal inverting the output of a Y decoder is impressed on a gate. CONSTITUTION:To a ROM involving a memory cell array 11, a Y selector for column line discharging 16 consisting of an N channel type MOS-FET connected to column lines D0-D3 and one voltage supplying terminal (GND) in which a signal which is outputs YD00-YD03 of a Y decoder 13 are inverted is impressed on respective gates is added. Thus, when the selected column line changes from the column line D0 to the column line D1, immediately after it is switched, the electric potential of the column line D0 which becomes non- selected for very short time loweres to a GND level, a period in which the electric potential of the newly selected column line D1 is lifted becomes very short, and adverse effect to delay charging up speed is eliminated. Thus, reading speed can be made high.
Bibliography:Application Number: JP19880135861