JP2522140B

A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode sign...

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Bibliographic Details
Main Authors NAKAMURA YOSHUKI, YOSHIDA MASAAKI
Format Patent
LanguageEnglish
Published 07.08.1996
Edition6
Subjects
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