JP2522140B
A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode sign...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
07.08.1996
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Edition | 6 |
Subjects | |
Online Access | Get full text |
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