JP2522140B

• Main Authors: NAKAMURA YOSHUKI, YOSHIDA MASAAKI
• Format: Patent
• Language: English
• Published: 07.08.1996
• Edition: 6
• Subjects: MEASURING; MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES; PHYSICS; TESTING

A logic circuit associated with a scan path circuit includes at least one clock controller and at least one scan flipflop. The clock controller includes a first control gate receiving a clock signal and a scan mode signal and configured to maintain its output at a fixed value when the scan mode signal is active, a second control gate receiving an output of the first control gate and a first test clock signal for generating a first enable signal, and a third control gate receiving an output of the second control gate and a second test clock signal for generating a second enable signal. The scan flipflop includes a selector having a pair of inputs receiving a data input signal and a scan input signal, respectively, and also having a selection input receiving the scan mode signal so that when the scan mode signal is active, the scan input signal is selected, and when the scan mode signal is inactive, the data input signal is selected. A first latch circuit receives an output of the selector at its data input and the first enable signal at its enable terminal. A second latch circuit receives an output of the first latch circuit at its data input and the second enable signal at its enable terminal.