MULTILAYER WIRING BOARD

• Main Authors: NISHIDA TOMOHIRO, JIN GUANGZHU, SHIRAKI FUMIO, HASEGAWA TATSUYA
• Format: Patent
• Language: English; Japanese
• Published: 27.10.2022
• Subjects: BASIC ELECTRIC ELEMENTS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS; PRINTED CIRCUITS; SEMICONDUCTOR DEVICES

To speed up communication between elements mounted on a multilayer wiring board.SOLUTION: A multilayer wiring board includes a ceramic substrate, a first wiring layer portion provided on the upper surface of the ceramic substrate, and a second wiring layer portion provided on the upper surface of the first wiring layer portion, a pad provided on the upper surface of the second wiring layer portion and a pad provided on the lower surface of the ceramic substrate are electrically connected, the second wiring layer portion has an element mounting area for mounting an element on the upper surface, and the plurality of the second wiring layer portions are provided on the upper surface of the first wiring layer portion, and the element mounting areas of at least two of the plurality of second wiring layer portion are electrically connected to each other by a first connecting wiring formed inside the first wiring layer portion.SELECTED DRAWING: Figure 2 【課題】多層配線基板に搭載された素子間での通信を高速化する。【解決手段】セラミック基板と、セラミック基板の上面に設けられた第１配線層部と、第１配線層部の上面に設けられた第２配線層部と、を有し、第２配線層部の上面に設けられたパッドとセラミック基板の下面に設けられたパッドとが電気的に接続されている多層配線基板では、第２配線層部は、素子を搭載するための素子搭載エリアを自身の上面に有するとともに、第１配線層部の上面に複数設けられており、複数の第２配線層部のうち少なくとも２つは、第１配線層部の内部に形成される第１連結配線によって、互いに有する素子搭載エリアが電気的に接続されている。【選択図】図２