SEMICONDUCTOR STORAGE DEVICE

• Main Author: INUZUKA YUKI
• Format: Patent
• Language: English; Japanese
• Published: 03.10.2022
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

To provide a storage device capable of being miniaturized by reducing the number of transistors.SOLUTION: A semiconductor storage device includes a plurality of first wirings and a plurality of second wirings. First and second transistors are connected to one or more first wirings and transmit a first voltage and a second voltage lower than the first voltage to the first wirings, respectively. Third and fourth transistors are connected to the plurality of second wirings and transmit the first voltage and the second voltage to the second wirings, respectively. A first memory cell includes a first diode and a first memory element connected in series and the first diode is connected in a forward bias direction from the first wiring toward a first signal line between the first signal line and the first wiring of the second wiring. A second memory cell includes a second diode and a second memory element connected in series and the second diode is connected in the forward bias direction from a second signal line to the first wiring between the second signal line and the first wiring of the second wiring.SELECTED DRAWING: Figure 4 【課題】トランジスタ数を減らし微細化可能な記憶装置を提供する。【解決手段】半導体記憶装置は、複数の第１配線と、複数の第２配線とを備える。第１および第２トランジスタは、１または複数の第１配線に接続され、第１電圧および第１電圧よりも低い第２電圧をそれぞれ第１配線に伝達する。第３および第４トランジスタは、複数の第２配線に接続され、第１および第２電圧をそれぞれ第２配線に伝達する。第１メモリセルは、直列に接続された第１ダイオードおよび第１メモリ素子を含み、第２配線のうち第１信号線と第１配線との間において該第１配線から該第１信号線へ向かって第１ダイオードが順バイアス方向に接続されている。第２メモリセルは、直列に接続された第２ダイオードおよび第２メモリ素子を含み、第２配線のうち第２信号線と第１配線との間において第２信号線から第１配線へ向かって第２ダイオードが順バイアス方向に接続されている。【選択図】図４