MEMORY SYSTEM

• Main Authors: YAMADA HIDEKI, SHIRAKAWA MASANOBU
• Format: Patent
• Language: English; Japanese
• Published: 11.03.2022
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

To provide a memory system that achieves improved reliability.SOLUTION: According to the embodiment, a memory system includes a semiconductor storage device 100 and a memory controller 200 that controls a read operation in the semiconductor storage device. The semiconductor storage device includes first and second memory cells MC0 stacked on a substrate, a word line WL0 connected to the first and second memory cells, a first bit line BL0 connected to the first memory cell, and a second bit line BL1 connected to the second memory cell. The read operation of a first state ("A") includes first and second read operations for reading data from the first and second memory cells, respectively. A first read voltage VA0 is applied to the word line during a first period in which the first read operation is performed, and a second read voltage VA1 is applied to the word line during a second period in which the second read operation is performed.SELECTED DRAWING: Figure 14 【課題】信頼性を向上する。【解決手段】実施形態によれば、メモリシステムは、半導体記憶装置１００と、半導体記憶装置における読み出し動作を制御するメモリコントローラ２００とを含む。半導体記憶装置は、基板の上方に積層された第１及び第２メモリセルＭＣ０と、第１及び第２メモリセルに接続されたワード線ＷＬ０と、第１メモリセルに接続された第１ビット線ＢＬ０と、第２メモリセルに接続された第２ビット線ＢＬ１とを含む。第１ステート（"Ａ"）の読み出し動作は、第１及び第２メモリセルのデータをそれぞれ読み出す第１及び第２読み出し動作を含む。第１読み出し動作を行う第１期間に、ワード線に第１読み出し電圧ＶＡ０が印加され、第２読み出し動作を行う第２期間に、ワード線に第２読み出し電圧ＶＡ１が印加される。【選択図】図１４