NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
To provide a highly-reliable nonvolatile semiconductor storage device capable of suppressing a leak current of a semiconductor substrate.SOLUTION: A nonvolatile semiconductor storage device 20 comprises: a semiconductor substrate 30 having a first conductivity type and including a crushed layer 30R...
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Main Authors | , |
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Format | Patent |
Language | English Japanese |
Published |
18.03.2021
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Subjects | |
Online Access | Get full text |
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Summary: | To provide a highly-reliable nonvolatile semiconductor storage device capable of suppressing a leak current of a semiconductor substrate.SOLUTION: A nonvolatile semiconductor storage device 20 comprises: a semiconductor substrate 30 having a first conductivity type and including a crushed layer 30R on a rear surface; a memory cell array 21 arranged on a surface facing the crushed layer of the semiconductor substrate; and a high-voltage transistor HVP of the first conductivity type arranged on the semiconductor substrate, including a channel of the first conductivity type, and supplying a high voltage to the memory cell array. The high-voltage transistor of the first conductivity type comprises a well region NW arranged on a surface of the semiconductor substrate and having a second conductivity type, which is an opposite conductivity type of the first conductivity type, a p+ source region and a p+ drain region arranged in the well region, and a first high concentration layer WT2 of the first conductivity type arranged between the crushed layer and the well region of the semiconductor substrate and having higher concentration than impurity concentration of the semiconductor substrate.SELECTED DRAWING: Figure 15
【課題】半導体基板のリーク電流を抑制し、高信頼性の不揮発性半導体記憶装置を提供する。【解決手段】不揮発性半導体記憶装置20は、第1導電型を有し、裏面に破砕層30Rを備える半導体基板30と、半導体基板の破砕層に対向する表面上に配置されたメモリセルアレイ21と、半導体基板上に配置され、第1導電型のチャネルを備え、メモリセルアレイに高電圧を供給する第1導電型高電圧トランジスタHVPとを備える。第1導電型高電圧トランジスタは、半導体基板の表面に配置され、第1導電型と反対導電型の第2導電型を有するウェル領域NWと、ウェル領域に配置されたp+ソース領域及びp+ドレイン領域と、半導体基板の破砕層とウェル領域との間に配置され、半導体基板の不純物濃度よりも高濃度の第1導電型の第1高濃度層WT2とを備える。【選択図】図15 |
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Bibliography: | Application Number: JP20190163798 |