LIQUID CRYSTAL DISPLAY DEVICE

To provide a liquid crystal display device which can suppress the reduction in the image quality.SOLUTION: A liquid crystal display device 1 comprises: a transistor 10 and a pixel electrode 20 which are provided in each of a plurality of pixels PX; a plurality of common electrodes 30 which are array...

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Bibliographic Details
Main Author KAJITA DAISUKE
Format Patent
LanguageEnglish
Japanese
Published 03.09.2020
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Summary:To provide a liquid crystal display device which can suppress the reduction in the image quality.SOLUTION: A liquid crystal display device 1 comprises: a transistor 10 and a pixel electrode 20 which are provided in each of a plurality of pixels PX; a plurality of common electrodes 30 which are arrayed in each of the first direction and the second direction, each of which faces one or more pixel electrodes 20 and which are provided so as to be separated from each other; a plurality of gate lines 40 which extend along the first direction; a plurality of gate lead-out lines 41 which extend in the second direction and are connected to the gate lines 40; and a plurality of data lines 50 which extend along the second direction. The plurality of gate lines 40 are provided two by two for each boundary of the two pixels PX adjacent to each other in the second direction. The plurality of pixels PX are formed of the plurality of pixels which are arrayed repeatedly in a periodic manner along the first direction. The plurality of data lines 50 and the plurality of gate lead-out lines 41 are formed on the same layer and provided repeatedly in a periodic manner for each boundary of the two pixels PX adjacent to each other in the first direction.SELECTED DRAWING: Figure 2 【課題】画像品位が低下することを抑制できる液晶表示装置を提供する。【解決手段】液晶表示装置1は、複数の画素PXの各々に設けられたトランジスタ10及び画素電極20と、第1方向及び第2方向の各々に配列され、各々が1つ以上の画素電極20に対向するとともに互いに分離して設けられた複数の共通電極30と、第1方向に沿って延在する複数のゲート線40と、第2方向に延在し、ゲート線40に接続される複数のゲート引出線41と、第2方向に沿って延在する複数のデータ線50とを備え、複数のゲート線40は、第2方向に隣り合う2つの画素PXの境界部ごとに2本ずつ設けられ、複数の画素PXは、第1方向に沿って周期的に繰り返して配列された複数種の画素によって構成されており、複数のデータ線50と複数のゲート引出線41とは、同層に形成されており、かつ、第1方向に隣り合う2つの画素PXの境界部ごとに周期的に繰り返して設けられている。【選択図】図2
Bibliography:Application Number: JP20190035901