IMAGE FORMING APPARATUS AND SUBSTRATE

To suppress the size of a wiring area as compared with a case in which a power supply voltage is applied to a semiconductor integrated circuit having a plurality of elements having different magnitudes of transient current fluctuations through a rectangular terminal when a power supply voltage is ap...

Full description

Saved in:
Bibliographic Details
Main Author KAWASHIMA SHIMPEI
Format Patent
LanguageEnglish
Japanese
Published 02.04.2020
Subjects
Online AccessGet full text

Cover

Loading…
Abstract To suppress the size of a wiring area as compared with a case in which a power supply voltage is applied to a semiconductor integrated circuit having a plurality of elements having different magnitudes of transient current fluctuations through a rectangular terminal when a power supply voltage is applied to the semiconductor integrated circuit.SOLUTION: An image forming apparatus includes a substrate on which a semiconductor integrated circuit having a plurality of elements having different magnitudes of transient current fluctuations is mounted, a ground terminal grounded on the back surface of a region where the semiconductor integrated circuit is mounted on the substrate, a large fluctuation terminal that is provided along the outer periphery of the ground terminal and applies a voltage to an element having a large transient current fluctuation from among the plurality of elements, and a small fluctuation terminal that is provided along the large fluctuation terminal on the opposite side to the ground terminal across the large fluctuation terminal and applies a voltage to an element having a small transient current fluctuation from among the plurality of elements.SELECTED DRAWING: Figure 6 【課題】過渡的な電流変動の大きさが異なる素子を複数有する半導体集積回路に電源電圧を印加する際、長方形状の端子を介してこの半導体集積回路に電源電圧を印加する場合と比較して、配線面積を抑制する。【解決手段】過渡的な電流変動の大きさが異なる複数の素子を有する半導体集積回路を搭載する基板と、基板における半導体集積回路が搭載されている領域の裏面に接地して設けられる接地端子と、接地端子の外周に沿って設けられ、複数の素子のうち過渡的な電流変動が大きい素子に電圧を印加する大変動端子と、大変動端子を挟んで接地端子とは反対側において大変動端子に沿って設けられ、複数の素子のうち過渡的な電流変動が小さい素子に電圧を印加する小変動端子とを備える画像形成装置。【選択図】図6
AbstractList To suppress the size of a wiring area as compared with a case in which a power supply voltage is applied to a semiconductor integrated circuit having a plurality of elements having different magnitudes of transient current fluctuations through a rectangular terminal when a power supply voltage is applied to the semiconductor integrated circuit.SOLUTION: An image forming apparatus includes a substrate on which a semiconductor integrated circuit having a plurality of elements having different magnitudes of transient current fluctuations is mounted, a ground terminal grounded on the back surface of a region where the semiconductor integrated circuit is mounted on the substrate, a large fluctuation terminal that is provided along the outer periphery of the ground terminal and applies a voltage to an element having a large transient current fluctuation from among the plurality of elements, and a small fluctuation terminal that is provided along the large fluctuation terminal on the opposite side to the ground terminal across the large fluctuation terminal and applies a voltage to an element having a small transient current fluctuation from among the plurality of elements.SELECTED DRAWING: Figure 6 【課題】過渡的な電流変動の大きさが異なる素子を複数有する半導体集積回路に電源電圧を印加する際、長方形状の端子を介してこの半導体集積回路に電源電圧を印加する場合と比較して、配線面積を抑制する。【解決手段】過渡的な電流変動の大きさが異なる複数の素子を有する半導体集積回路を搭載する基板と、基板における半導体集積回路が搭載されている領域の裏面に接地して設けられる接地端子と、接地端子の外周に沿って設けられ、複数の素子のうち過渡的な電流変動が大きい素子に電圧を印加する大変動端子と、大変動端子を挟んで接地端子とは反対側において大変動端子に沿って設けられ、複数の素子のうち過渡的な電流変動が小さい素子に電圧を印加する小変動端子とを備える画像形成装置。【選択図】図6
Author KAWASHIMA SHIMPEI
Author_xml – fullname: KAWASHIMA SHIMPEI
BookMark eNrjYmDJy89L5WRQ9fR1dHdVcPMP8vX0c1dwDAhwDHIMCQ1WcPRzUQgOdQoOAXJdeRhY0xJzilN5oTQ3g5Kba4izh25qQX58anFBYnJqXmpJvFeAkYGRgYGpsYmlkaMxUYoAyCAlag
ContentType Patent
DBID EVB
DatabaseName esp@cenet
DatabaseTitleList
Database_xml – sequence: 1
  dbid: EVB
  name: esp@cenet
  url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP
  sourceTypes: Open Access Repository
DeliveryMethod fulltext_linktorsrc
Discipline Medicine
Chemistry
Sciences
DocumentTitleAlternate 画像形成装置および基板
ExternalDocumentID JP2020053492A
GroupedDBID EVB
ID FETCH-epo_espacenet_JP2020053492A3
IEDL.DBID EVB
IngestDate Fri Aug 23 06:56:16 EDT 2024
IsOpenAccess true
IsPeerReviewed false
IsScholarly false
Language English
Japanese
LinkModel DirectLink
MergedId FETCHMERGED-epo_espacenet_JP2020053492A3
Notes Application Number: JP20180179571
OpenAccessLink https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200402&DB=EPODOC&CC=JP&NR=2020053492A
ParticipantIDs epo_espacenet_JP2020053492A
PublicationCentury 2000
PublicationDate 20200402
PublicationDateYYYYMMDD 2020-04-02
PublicationDate_xml – month: 04
  year: 2020
  text: 20200402
  day: 02
PublicationDecade 2020
PublicationYear 2020
RelatedCompanies FUJI XEROX CO LTD
RelatedCompanies_xml – name: FUJI XEROX CO LTD
Score 3.383379
Snippet To suppress the size of a wiring area as compared with a case in which a power supply voltage is applied to a semiconductor integrated circuit having a...
SourceID epo
SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
CORRECTION OF TYPOGRAPHICAL ERRORS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME
LINING MACHINES
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PERFORMING OPERATIONS
PRINTED CIRCUITS
PRINTING
SELECTIVE PRINTING MECHANISMS
SEMICONDUCTOR DEVICES
STAMPS
TRANSPORTING
TYPEWRITERS
Title IMAGE FORMING APPARATUS AND SUBSTRATE
URI https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200402&DB=EPODOC&locale=&CC=JP&NR=2020053492A
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp6JOpYj2rdh1adc-FOnntkK7sLWyt2H6ASrocBX_fS-x0z3tLcnB5YvL3S-5uwDclb2BSgqiKqVeMIUYrFRYzlPu60afEY6Dch6NHCfGKCPRXJ-34G0dCyPyhH6L5IgoUTnKey3O6-X_JZYvfCtXD-wFmz4ew9T25QYd8y1XNdl37YBO_Ikne54dUTmZ_tJ0norP2YFdtKMHXByCJ5eHpSw3dUp4BHsU2b3Xx9B6fe7Agbf-eq0D-3Hz4o3FRvhWJ3A_jp1hICFsi8fJUHIodaZOms0kJ_GlWeby74_T4BRuwyD1Rgr2t_ib3SKiG2Prn0EbYX95DlKlmYaF-NHIdYsURWVWpKdWaI4Ri5mFWV1Adwujy63ULhzymvBA0a6gXX9-ldeoXGt2IxblB9bVeGM
link.rule.ids 230,309,783,888,25576,76876
linkProvider European Patent Office
linkToHtml http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT4NAEJ7Uaqw3rRq1PohRbkRKFwoHYngWsNBNC6Y30uWRqIk2FuPfdxep9tTbZieZfWV25tudB8Bd0R-KKEeiUMg5EZBCCoFkLOW-rAwIYjgoY9HIYaR4CQrm8rwFb-tYmDpP6HedHJFKVEblvarv6-X_I5Zd-1auHsgL7fp4dGPd5ht0zI5clHjb1B08sScWb1l6gPlo-kuTWSo-Ywd2qY09ZOLgPJssLGW5qVPcQ9jDlN17dQSt10UXOta69FoX9sPmx5s2G-FbHcO9Hxojh6OwLfSjEWdgbEyNOJlxRmRzs8Rk5Y9j5wRuXSe2PIGOl_6tLg3wxtwGp9CmsL84A66UVEWj-FHJZA3leamWqC-W1BxDGlFztTyH3hZGF1upN9Dx4nCcjv3oqQcHjFJ7o0iX0K4-v4orqmgrcl1v0A-nZntW
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=IMAGE+FORMING+APPARATUS+AND+SUBSTRATE&rft.inventor=KAWASHIMA+SHIMPEI&rft.date=2020-04-02&rft.externalDBID=A&rft.externalDocID=JP2020053492A