SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

To provide a semiconductor device that has a plurality of entirely resin-sealed semiconductor units connected in parallel on a conductor base and that has higher dielectric breakdown tolerance than before.SOLUTION: A semiconductor device comprises: a plurality of semiconductor modules on a metal bas...

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Main Author TANIGUCHI KATSUMI
Format Patent
LanguageEnglish
Japanese
Published 21.11.2019
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Abstract To provide a semiconductor device that has a plurality of entirely resin-sealed semiconductor units connected in parallel on a conductor base and that has higher dielectric breakdown tolerance than before.SOLUTION: A semiconductor device comprises: a plurality of semiconductor modules on a metal base (conductor base) 1; a first insulation bus bar 12a and a second insulation bus bar 12b connecting the semiconductor modules; a box type insulation resin frame 9 at a periphery of the semiconductor modules; a first insulation layer 10 having a top surface at a position lower than upper ends of terminals 6a-6f extending from insulation circuit boards (2, 3 and 4) of the semiconductor module inside the insulation resin frame 9; and second insulation layers 13a-13c having upper ends of the terminals 6a-6f buried inside the insulation resin frame 9 and on the first insulation layer 10, wherein an interface formed of the first insulation layer 10, the second insulation layers 13a-13c, and a side wall part (third insulation layer) of the insulation resin frame 9 is arranged between the terminals 6a-6f and a lower end of the side wall part at a grounding position.SELECTED DRAWING: Figure 2 【課題】導体ベース上に全体が樹脂封止された半導体ユニットを複数並列接続させた半導体装置であって、絶縁破壊耐性を従来よりも高めた半導体装置を提供する。【解決手段】金属ベース(導体ベース)1上の複数の半導体モジュールと、半導体モジュール間を接続する第1絶縁ブスバー12a及び第2絶縁ブスバー12bと、半導体モジュールの周囲の箱型の絶縁樹脂枠9と、絶縁樹脂枠9の内側の半導体モジュールの絶縁回路基板(2,3,4)から延びる端子6a〜6fの上端よりも低い位置に上面を有して半導体モジュールを封止する第1の絶縁層10と、絶縁樹脂枠9の内側で第1の絶縁層10の上に、端子6a〜6fの上端が埋め込まれる第2の絶縁層13a〜13cとを備え、端子6a〜6fと、接地位置をなす側壁部の下端との間に、第1の絶縁層10、第2の絶縁層13a〜13c及び絶縁樹脂枠9の側壁部(第3の絶縁層)によって形成された界面が配置される。【選択図】図2
AbstractList To provide a semiconductor device that has a plurality of entirely resin-sealed semiconductor units connected in parallel on a conductor base and that has higher dielectric breakdown tolerance than before.SOLUTION: A semiconductor device comprises: a plurality of semiconductor modules on a metal base (conductor base) 1; a first insulation bus bar 12a and a second insulation bus bar 12b connecting the semiconductor modules; a box type insulation resin frame 9 at a periphery of the semiconductor modules; a first insulation layer 10 having a top surface at a position lower than upper ends of terminals 6a-6f extending from insulation circuit boards (2, 3 and 4) of the semiconductor module inside the insulation resin frame 9; and second insulation layers 13a-13c having upper ends of the terminals 6a-6f buried inside the insulation resin frame 9 and on the first insulation layer 10, wherein an interface formed of the first insulation layer 10, the second insulation layers 13a-13c, and a side wall part (third insulation layer) of the insulation resin frame 9 is arranged between the terminals 6a-6f and a lower end of the side wall part at a grounding position.SELECTED DRAWING: Figure 2 【課題】導体ベース上に全体が樹脂封止された半導体ユニットを複数並列接続させた半導体装置であって、絶縁破壊耐性を従来よりも高めた半導体装置を提供する。【解決手段】金属ベース(導体ベース)1上の複数の半導体モジュールと、半導体モジュール間を接続する第1絶縁ブスバー12a及び第2絶縁ブスバー12bと、半導体モジュールの周囲の箱型の絶縁樹脂枠9と、絶縁樹脂枠9の内側の半導体モジュールの絶縁回路基板(2,3,4)から延びる端子6a〜6fの上端よりも低い位置に上面を有して半導体モジュールを封止する第1の絶縁層10と、絶縁樹脂枠9の内側で第1の絶縁層10の上に、端子6a〜6fの上端が埋め込まれる第2の絶縁層13a〜13cとを備え、端子6a〜6fと、接地位置をなす側壁部の下端との間に、第1の絶縁層10、第2の絶縁層13a〜13c及び絶縁樹脂枠9の側壁部(第3の絶縁層)によって形成された界面が配置される。【選択図】図2
Author TANIGUCHI KATSUMI
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Snippet To provide a semiconductor device that has a plurality of entirely resin-sealed semiconductor units connected in parallel on a conductor base and that has...
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SourceType Open Access Repository
SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
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