SEMICONDUCTOR DEVICE

To provide a semiconductor device capable of suppressing a crystal defect in a semiconductor layer.SOLUTION: A semiconductor device 1 includes a semiconductor layer 51 having an n-type MIS region 61 partitioned by a first trench 71, a first trench insulating layer 72 formed in the first trench 71, a...

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Main Authors OKUDA HAJIME, FUKUDA YOSHINORI
Format Patent
LanguageEnglish
Japanese
Published 09.05.2019
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Abstract To provide a semiconductor device capable of suppressing a crystal defect in a semiconductor layer.SOLUTION: A semiconductor device 1 includes a semiconductor layer 51 having an n-type MIS region 61 partitioned by a first trench 71, a first trench insulating layer 72 formed in the first trench 71, a first field insulating layer 76 formed on a first major surface 52 of the semiconductor layer 51 at a distance from the first trench 71 toward the inward portion of the n-type MIS region 61 and covering the n-type MIS region 61, and a first bridge insulating layer 79 formed in a region between the first trench 71 and the first field insulation layer 76 on the first major surface 52 of the semiconductor layer 51 and connected to the first trench insulation layer 72 and the first field insulation layer 76.SELECTED DRAWING: Figure 4 【課題】半導体層の結晶欠陥を抑制できる半導体装置を提供する。【解決手段】半導体装置1は、第1トレンチ71によって区画されたn型MIS領域61を有する半導体層51と、第1トレンチ71内に形成された第1トレンチ絶縁層72と、半導体層51の第1主面52において第1トレンチ71からn型MIS領域61の内方部側に間隔を空けて形成され、n型MIS領域61を被覆する第1フィールド絶縁層76と、半導体層51の第1主面52において第1トレンチ71および第1フィールド絶縁層76の間の領域に形成され、第1トレンチ絶縁層72および第1フィールド絶縁層76に連結された第1ブリッジ絶縁層79と、を含む。【選択図】図4
AbstractList To provide a semiconductor device capable of suppressing a crystal defect in a semiconductor layer.SOLUTION: A semiconductor device 1 includes a semiconductor layer 51 having an n-type MIS region 61 partitioned by a first trench 71, a first trench insulating layer 72 formed in the first trench 71, a first field insulating layer 76 formed on a first major surface 52 of the semiconductor layer 51 at a distance from the first trench 71 toward the inward portion of the n-type MIS region 61 and covering the n-type MIS region 61, and a first bridge insulating layer 79 formed in a region between the first trench 71 and the first field insulation layer 76 on the first major surface 52 of the semiconductor layer 51 and connected to the first trench insulation layer 72 and the first field insulation layer 76.SELECTED DRAWING: Figure 4 【課題】半導体層の結晶欠陥を抑制できる半導体装置を提供する。【解決手段】半導体装置1は、第1トレンチ71によって区画されたn型MIS領域61を有する半導体層51と、第1トレンチ71内に形成された第1トレンチ絶縁層72と、半導体層51の第1主面52において第1トレンチ71からn型MIS領域61の内方部側に間隔を空けて形成され、n型MIS領域61を被覆する第1フィールド絶縁層76と、半導体層51の第1主面52において第1トレンチ71および第1フィールド絶縁層76の間の領域に形成され、第1トレンチ絶縁層72および第1フィールド絶縁層76に連結された第1ブリッジ絶縁層79と、を含む。【選択図】図4
Author OKUDA HAJIME
FUKUDA YOSHINORI
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Snippet To provide a semiconductor device capable of suppressing a crystal defect in a semiconductor layer.SOLUTION: A semiconductor device 1 includes a semiconductor...
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SubjectTerms BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Title SEMICONDUCTOR DEVICE
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