ELECTRODE FORMATION METHOD, AND ELECTRODE STRUCTURE OF SEMICONDUCTOR ELEMENT

• Main Authors: HAYASHI SHIGEHIRO, NOKITA KANTA, KATO YOSHINAO, HAN YOUNGGUN, HORIUCHI HITOSHI
• Format: Patent
• Language: English; Japanese
• Published: 27.12.2018
• Subjects: BASIC ELECTRIC ELEMENTS; CHEMICAL SURFACE TREATMENT; CHEMISTRY; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATIONOR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY IONIMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; COATING MATERIAL WITH METALLIC MATERIAL; COATING METALLIC MATERIAL; DIFFUSION TREATMENT OF METALLIC MATERIAL; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION INGENERAL; METALLURGY; SEMICONDUCTOR DEVICES; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THESURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION

To provide an electrode formation method for forming an electrode structure suitable for being built in a printed circuit board in few steps using electroless plating, and an electrode structure of a semiconductor element.SOLUTION: In an electrode formation method for forming an electrode of a semiconductor element for being built in a printed circuit board, a Cu (copper) layer laminated on a buffer layer is formed by electroless plating, the buffer layer being laminated on an Al electrode or an Al alloy electrode which is a surface electrode of a wafer after circuit formation, and the semiconductor element is thus formed. The buffer layer may be formed by electroless Ni plating, or may be subjected to Au substitution treatment to cover the Ni layer with an Au layer.SELECTED DRAWING: Figure 1 【課題】無電解めっきを利用した少ない工程数でプリント基板の内蔵用に適した電極構造を形成する電極形成方法及び半導体素子電極構造を提供する。【解決手段】プリント基板に内蔵する半導体素子の電極を形成する電極形成方法であって、半導体素子、又は回路形成後のウエハの表面電極であるＡｌ電極又はＡｌ合金電極に積層されるバッファ層に対して、当該バッファ層を被覆して積層されるＣｕ（銅）層を無電解めっきで形成する。また、このバッファ層は無電解Ｎｉめっき処理で形成されてもよいし、Ｎｉ層をさらにＡｕ層で被覆するように置換Ａｕ処理を行ってもよい。【選択図】図１