CHIP RESISTOR AND MANUFACTURING METHOD OF THE SAME
PROBLEM TO BE SOLVED: To provide a technique for suppressing change over time in a resistance value in a chip resistor.SOLUTION: The chip resistor includes: an insulating substrate; a thin film resistor formed on the substrate; a pair of electrodes connected to the thin film resistor; and at least a...
Saved in:
| Main Author | |
|---|---|
| Format | Patent |
| Language | English Japanese |
| Published |
03.08.2017
|
| Subjects | |
| Online Access | Get full text |
Cover
Loading…
| Abstract | PROBLEM TO BE SOLVED: To provide a technique for suppressing change over time in a resistance value in a chip resistor.SOLUTION: The chip resistor includes: an insulating substrate; a thin film resistor formed on the substrate; a pair of electrodes connected to the thin film resistor; and at least a protective film covering the thin film resistor between the pair of electrodes. The protective film includes: a first protective film made of silicon nitride in contact with the thin film resistor; and a second protective film made of silicon oxide in contact with the first protective film.SELECTED DRAWING: Figure 3
【課題】チップ抵抗器における抵抗値の経時変化を抑制する技術を提供する。【解決手段】絶縁性の基板と、前記基板上に形成された薄膜抵抗体と、前記薄膜抵抗体と接続された一対の電極と、少なくとも、前記一対の電極間における前記薄膜抵抗体を覆う保護膜と、を備え、前記保護膜は、前記薄膜抵抗体に接する窒化シリコンからなる第１の保護膜と、前記第１の保護膜に接する酸化シリコンからなる第２の保護膜と、を含む、薄膜チップ抵抗器。【選択図】図３ |
|---|---|
| AbstractList | PROBLEM TO BE SOLVED: To provide a technique for suppressing change over time in a resistance value in a chip resistor.SOLUTION: The chip resistor includes: an insulating substrate; a thin film resistor formed on the substrate; a pair of electrodes connected to the thin film resistor; and at least a protective film covering the thin film resistor between the pair of electrodes. The protective film includes: a first protective film made of silicon nitride in contact with the thin film resistor; and a second protective film made of silicon oxide in contact with the first protective film.SELECTED DRAWING: Figure 3
【課題】チップ抵抗器における抵抗値の経時変化を抑制する技術を提供する。【解決手段】絶縁性の基板と、前記基板上に形成された薄膜抵抗体と、前記薄膜抵抗体と接続された一対の電極と、少なくとも、前記一対の電極間における前記薄膜抵抗体を覆う保護膜と、を備え、前記保護膜は、前記薄膜抵抗体に接する窒化シリコンからなる第１の保護膜と、前記第１の保護膜に接する酸化シリコンからなる第２の保護膜と、を含む、薄膜チップ抵抗器。【選択図】図３ |
| Author | HIROSHIMA YASUSHI |
| Author_xml | – fullname: HIROSHIMA YASUSHI |
| BookMark | eNrjYmDJy89L5WQwcvbwDFAIcg32DA7xD1Jw9HNR8HX0C3VzdA4JDfL0c1fwdQ3x8HdR8HdTCPFwVQh29HXlYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBobmhsamRsYmjsZEKQIAr5goxg |
| ContentType | Patent |
| DBID | EVB |
| DatabaseName | esp@cenet |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Medicine Chemistry Sciences |
| DocumentTitleAlternate | チップ抵抗器およびその製造方法 |
| ExternalDocumentID | JP2017135234A |
| GroupedDBID | EVB |
| ID | FETCH-epo_espacenet_JP2017135234A3 |
| IEDL.DBID | EVB |
| IngestDate | Fri Aug 30 05:42:20 EDT 2024 |
| IsOpenAccess | true |
| IsPeerReviewed | false |
| IsScholarly | false |
| Language | English Japanese |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-epo_espacenet_JP2017135234A3 |
| Notes | Application Number: JP20160013252 |
| OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170803&DB=EPODOC&CC=JP&NR=2017135234A |
| ParticipantIDs | epo_espacenet_JP2017135234A |
| PublicationCentury | 2000 |
| PublicationDate | 20170803 |
| PublicationDateYYYYMMDD | 2017-08-03 |
| PublicationDate_xml | – month: 08 year: 2017 text: 20170803 day: 03 |
| PublicationDecade | 2010 |
| PublicationYear | 2017 |
| RelatedCompanies | KOA CORP |
| RelatedCompanies_xml | – name: KOA CORP |
| Score | 3.219246 |
| Snippet | PROBLEM TO BE SOLVED: To provide a technique for suppressing change over time in a resistance value in a chip resistor.SOLUTION: The chip resistor includes: an... |
| SourceID | epo |
| SourceType | Open Access Repository |
| SubjectTerms | BASIC ELECTRIC ELEMENTS ELECTRICITY RESISTORS |
| Title | CHIP RESISTOR AND MANUFACTURING METHOD OF THE SAME |
| URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170803&DB=EPODOC&locale=&CC=JP&NR=2017135234A |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dS8MwED_mFPVNp6JOJYj0rWjXuNWHIl3a0hX6wdbK3kbStaBCN1zFf99L2HRPe0tycEkOLve75O4C8GAKaghaWTqnValLAK8LxHB6JUq01iVidC7vO6K4H-Q0nD5PW_C5yYVRdUJ_VHFE1KgC9b1R5_Xy_xLLVbGVq0fxjkOLVz-zXW3tHRsDBECm5g5tL03chGmM2WGqxWNFMxBsmNTZg33E0QMZ_-W9DWVaynLbpvgncJAiu7o5hdYH78AR23y91oHDaP3ijc218q3OoMeCUUpQYqNJloyJE7skcuLcd1iWy5gGEnlZkLgk8UkWeGTiRN453PtexgIdJ5_9bXUWplsLNS-gXS_q8hIIfylkYToECxWnFn_iFS3m6FHOrT7vFVxcQXcHo-ud1C4cy56KajNvoN18fZe3aGkbcack9AuAQXyR |
| link.rule.ids | 230,309,783,888,25578,76884 |
| linkProvider | European Patent Office |
| linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV3dT8IwEL8gGvFNUaPiR2PM3haFVZwPxIxuy0D2ESiGN9KOLVETIDLjv--1GcoTb00vubaXXO9317srwJ0laVPS3DYFzTNTAXhTIoYzc5mhtc4QowsV7wijdjCm_cnjpAKf61oY3Sf0RzdHRI1KUd8LfV8v_4NYrs6tXN3Ld5xavPi84xqld9x8QgBkGW634yWxGzODsU4_MaKhpjURbFjU2YFdxNi2arTvvXVVWcpy06b4h7CXILt5cQSVD1GHGlt_vVaH_bB88cZhqXyrY2ixoJcQlFhvxOMhcSKXhE409h3GxyqngYQeD2KXxD7hgUdGTuidwK3vcRaYuPj076jTfrKxUesUqvPFPDsDIp5T1ZgOwUIuqC0eRE7TGXqUM7stWqmQ59DYwuhiK_UGagEPB9NBL3ptwIGi6Aw36xKqxdd3doVWt5DXWlq_f01_gQ |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=CHIP+RESISTOR+AND+MANUFACTURING+METHOD+OF+THE+SAME&rft.inventor=HIROSHIMA+YASUSHI&rft.date=2017-08-03&rft.externalDBID=A&rft.externalDocID=JP2017135234A |