MEMORY SYSTEM

PROBLEM TO BE SOLVED: To provide a memory system capable of reducing loads on a host device.SOLUTION: A memory system includes: a first pin that can receive a chip select signal from a host device; interface circuits that recognize as a command a signal which is received immediately after the chip s...

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Bibliographic Details
Main Authors KITAZUME TOSHIHIKO, KODERA SHUNSUKE, KADA KENICHIRO, IWATA TETSUYA, FURUYAMA YOSHIO, TSUJI NOBUHIRO, TAKEDA SHINYA, NARAI YOSUKE
Format Patent
LanguageEnglish
Japanese
Published 02.03.2017
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To provide a memory system capable of reducing loads on a host device.SOLUTION: A memory system includes: a first pin that can receive a chip select signal from a host device; interface circuits that recognize as a command a signal which is received immediately after the chip select signal is received; a memory cell array; and an error detection circuit. The interface circuits can transmit, to the host device, information BFS indicating that the number of error bits detected by any of first units has exceeded a predetermined threshold.SELECTED DRAWING: Figure 21 【課題】ホスト機器の負荷を軽減出来るメモリシステムを提供する。【解決手段】メモリシステムは、ホスト機器からチップセレクト信号を受信可能な第１ピンと、チップセレクト信号が受信された直後に受信された信号をコマンドとして認識するインターフェース回路と、メモリセルアレイと、エラー検出回路とを備える。インターフェース回路は、いずれかの第１単位で検出されたエラービット数が所定の閾値を超えたことを示す情報BFSをホスト機器へ送信可能である。【選択図】図２１
Bibliography:Application Number: JP20150169708