SEMICONDUCTOR MEMORY DEVICE

• Main Author: HOSONO KOJI
• Format: Patent
• Language: English; Japanese
• Published: 22.08.2016
• Subjects: INFORMATION STORAGE; PHYSICS; STATIC STORES

PROBLEM TO BE SOLVED: To provide a semiconductor memory device that can improve operation reliability.SOLUTION: A semiconductor memory device of an embodiment includes: first and second memory cells; a first word line connected to gates of the first and second memory cells; a first bit line electrically connected to one end of the first memory cell; and a second bit line electrically connected to one end of the second memory cell. A write operation includes a plurality of loops, which include: a first operation for applying a write voltage; a second operation for applying a first voltage lower than the write voltage; and a third operation for applying a verify voltage. When, in the third operation, a threshold voltage of the first memory cell is lower than a first threshold and a threshold voltage of the second memory cell is equal to or higher than the first threshold, a second voltage is applied to the first bit line and a third voltage lower than the second voltage is applied to the second bit line in the second operation.SELECTED DRAWING: Figure 5 【課題】動作信頼性を向上できる半導体記憶装置を提供する。【解決手段】実施形態の半導体記憶装置は、第１、第２メモリセルと、第１、第２メモリセルのゲートに接続された第１ワード線と、第１メモリセルの一端に電気的に接続された第１ビット線と、第２メモリセルの一端に電気的に接続された第２ビット線とを備える。書き込み動作は複数のループを含み、前記ループは書き込み電圧を印加する第１動作、書き込み電圧より低い第１電圧を印加する第２動作、及びベリファイ電圧を印加する第３動作を含む。前記第３動作において、第１メモリセルの閾値電圧が第１閾値より低く、第２メモリセルの閾値電圧が第１閾値以上であるとき、前記第２動作では、第１ビット線に第２電圧が印加され、第２ビット線に前記第２電圧より低い第３電圧が印加される。【選択図】図５