VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• Main Authors: NIIMURA YASUSHI, SAKATA TOSHIAKI
• Format: Patent
• Language: English; Japanese
• Published: 26.11.2015
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a vertical semiconductor device capable of obtaining a low on-resistance, a high avalanche resistance, a high turn-off resistance and a high reverse recovery resistance, and to provide a method of manufacturing the same.SOLUTION: A vertical semiconductor device that comprises an element active part and a withstanding voltage structure part, comprises: a first main electrode and a gate pad electrode on a first principal surface of the element active part; a first parallel pn layer on a drift layer at a lower part of the first main electrode; and a second parallel pn layer at a lower part of the gate pad electrode. Between the second parallel pn layer at the lower part of the gate pad electrode and a p well region arranged on a surface layer of the drift layer, a first conductivity type isolation region is provided. By setting a repetition pitch of the second parallel pn layer to be narrower than that of the first parallel pn layer, a low on-resistance, a high avalanche resistance, a high turn-off resistance and a high reverse recovery resistance can be obtained. 【課題】低オン抵抗、高アバランシェ耐量、高ターンオフ耐量および高逆回復耐量を得ることができる縦型半導体装置およびその製造方法を提供する。【解決手段】素子活性部と耐圧構造部を備えた縦型半導体装置において、素子活性部の第１主面には第１の主電極とゲートパッド電極を有し、第１の主電極下部のドリフト層には、第１並列ｐｎ層を備え、ゲートパッド電極下部には、第２並列ｐｎ層を備える。ゲートパッド電極下部の第２並列ｐｎ層とドリフト層の表面層に配置されたｐウェル領域との間には第１導電型分離領域を備え、第２並列ｐｎ層の繰り返しピッチは第１並列ｐｎ層の繰り返しピッチより狭くすることで、低オン抵抗、高アバランシェ耐量、高ターンオフ耐量および高逆回復耐量を得ることができる。【選択図】 図２