SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

• Main Authors: FUJIWARA TAKESHI, NAGAKURA KOTARO
• Format: Patent
• Language: English; Japanese
• Published: 17.11.2014
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a semiconductor device including a metal element in which variation in physical property is inhibited; and provide a semiconductor device manufacturing method which has reduced number of manufacturing processes of the semiconductor device in comparison with prior art.SOLUTION: A semiconductor device 1 of the present invention comprises: a first oxidized species entry prevention cover 11 formed on a substrate 10; a first interlayer insulation film 12 which covers the first oxidized species entry prevention cover 11; a TaN resistive element 13 formed on the first interlayer insulation film 12; a second interlayer insulation film 15 which covers the TaN resistive element 13; a pair of metal plugs 16 which are connected to both ends of the TaN resistive element 13; a pair of metal wirings 19 respectively connected to the metal plugs 16; and a second oxidized species entry prevention cover 18 formed on the second interlayer insulation film 15 separately from each metal wiring 19. The TaN resistive element 13 overlaps the first oxidized species entry prevention cover 11 in planar view and the TaN resistive element 13 between the metal plugs 16 overlaps the second oxidized species entry prevention cover 18 in planar view. 【課題】物性値の変動を抑制した金属素子を備えた半導体装置及びその製造工程の数を従来技術と比べて低減した半導体装置の製造方法を提供する。【解決手段】本願発明の半導体装置１は、基板１０上に形成された第１の酸化種侵入防止用カバー１１と、第１の酸化種侵入防止用カバー１１を覆った第１の層間絶縁膜１２と、第１の層間絶縁膜１２上に形成されたＴａＮ抵抗体１３と、ＴａＮ抵抗体１３を覆った第２の層間絶縁膜１５と、ＴａＮ抵抗体１３の両端部に接続された一対の金属プラグ１６と、各金属プラグ１６に接続された一対の金属配線１９と、各金属配線１９とは別の、第２の層間絶縁膜１５上に形成された第２の酸化種侵入防止用カバー１８とを備え、ＴａＮ抵抗体１３は平面視で第１の酸化種侵入防止用カバー１１と重なっており、金属プラグ１６同士の間のＴａＮ抵抗体１３は平面視で第２の酸化種侵入防止用カバー１８と重なっている。【選択図】図１