NON-VOLATILE SEMICONDUCTOR MEMORY AND VOLTAGE TRIMMING METHOD FOR THE SAME
PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory.SOLUTION: A non-volatile semiconductor memory includes: a plurality of blocks each of which has a plurality of memory cells; a plurality of bit lines; a plurality of sense amplifier circuits each of which has a firs...
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Format | Patent |
Language | English |
Published |
24.02.2014
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Abstract | PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory.SOLUTION: A non-volatile semiconductor memory includes: a plurality of blocks each of which has a plurality of memory cells; a plurality of bit lines; a plurality of sense amplifier circuits each of which has a first transistor; a plurality of second transistors arranged at positions close to the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a plurality of third transistors arranged at positions far from the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a source line; and a control circuit. The control circuit changes a voltage to be applied to the control line of the plurality of first transistors on the basis of a trimming voltage by which currents flowing in the control line to the plurality of second transistors and the plurality of third transistors are made the same when a first voltage is applied to the bit lines in accordance with the position of the selected block in which the plurality of selected memory cells are arranged. |
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AbstractList | PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory.SOLUTION: A non-volatile semiconductor memory includes: a plurality of blocks each of which has a plurality of memory cells; a plurality of bit lines; a plurality of sense amplifier circuits each of which has a first transistor; a plurality of second transistors arranged at positions close to the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a plurality of third transistors arranged at positions far from the sense amplifier circuits of the plurality of bit lines, and connected to each of the plurality of bit lines; a source line; and a control circuit. The control circuit changes a voltage to be applied to the control line of the plurality of first transistors on the basis of a trimming voltage by which currents flowing in the control line to the plurality of second transistors and the plurality of third transistors are made the same when a first voltage is applied to the bit lines in accordance with the position of the selected block in which the plurality of selected memory cells are arranged. |
Author | FUJIMURA SUSUMU |
Author_xml | – fullname: FUJIMURA SUSUMU |
BookMark | eNrjYmDJy89L5WTw8vP30w3z93EM8fRxVQh29fV09vdzCXUO8Q9S8HX19Q-KVHD0c1EAqghxdHdVCAny9PX19HMHyoV4-LsouAGVhXgANTr6uvIwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDQxMDY1NzczNHY6IUAQD6bS-0 |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences Physics |
ExternalDocumentID | JP2014035776A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JP2014035776A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 12:39:00 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JP2014035776A3 |
Notes | Application Number: JP20120176541 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140224&DB=EPODOC&CC=JP&NR=2014035776A |
ParticipantIDs | epo_espacenet_JP2014035776A |
PublicationCentury | 2000 |
PublicationDate | 20140224 |
PublicationDateYYYYMMDD | 2014-02-24 |
PublicationDate_xml | – month: 02 year: 2014 text: 20140224 day: 24 |
PublicationDecade | 2010 |
PublicationYear | 2014 |
RelatedCompanies | TOSHIBA CORP |
RelatedCompanies_xml | – name: TOSHIBA CORP |
Score | 2.922356 |
Snippet | PROBLEM TO BE SOLVED: To provide a highly reliable non-volatile semiconductor memory.SOLUTION: A non-volatile semiconductor memory includes: a plurality of... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | INFORMATION STORAGE PHYSICS STATIC STORES |
Title | NON-VOLATILE SEMICONDUCTOR MEMORY AND VOLTAGE TRIMMING METHOD FOR THE SAME |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140224&DB=EPODOC&locale=&CC=JP&NR=2014035776A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dT8Iw8IL4-aaoUVHTGLO3xTHKNh-IGVthLOwjsxB8IvsiMSaDyIx_31sF5YnH3rWX9pL7au-uAI_P80TNVa1KxWklMnrEmRwrNJbTVpbTdpLGRlxVI3u-5oypO-1Ma_CxqYURfUK_RXNElKgU5b0U-nr5f4lli9zK1VPyjqDFS593bWkdHWO0gCZJsntdFgZ2YEmW1XVDyY9-ce2OrmvmHuyjH61X-V9s0qvKUpbbNqV_CgchkivKM6jlRQOOrc3Xaw048tYv3g04FCma6QqBazFcnYProwKcBCOTD0eMvFasDHx7bPEgIh7zguiNmL5NcAY3B4zwaOh5Q3-AOO4ENsHAj3AHF5oeu4CHPuOWI-P2Zn_MmLnh1lHal1AvFkV-BUTTNcWgqpIqekzVrGPElKo00Q1l3sqzlF5Dcwehm53YJpxUI1HJTW-hXn5-5Xdoi8vkXvDwB_vRhhQ |
link.rule.ids | 230,309,783,888,25578,76884 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfV1LT8JAEJ4gPvCmqFHxsTGmN2IpS1sPxJS20NZu29TF4In0RWJMCpEa_77TCsqJ687uZHeSee3ONwtw_ziLpUySy1KcTtzGiDhtRyKN2kknzWg3TiI1KtHIzJOtMXUmvUkNPtZYmKpP6HfVHBE1KkF9Lyp7vfi_xDKq2srlQ_yOQ_OnIe8bwio7xmwBXZJgDPpm4Bu-Luh63wkEL_yldXuKIms7sIsxtlo22jdfByUsZbHpU4ZHsBcgu7w4hlqWN6Ghr79ea8IBW714N2G_KtFMlji4UsPlCTgeGsBX39W47ZrkpRSl7xljnfshYSbzwzeieQbBGVwbmYSHNmO2N0Iat3yDYOJHuIULNWaewt3Q5LrVxu1N_4QxdYKNo3TPoJ7P8-wciKzIokolMRGViEppT40olWisqOKsk6UJvYDWFkaXW6m30LA4c6eu7T234LCkVKhuegX14vMru0a_XMQ3lTx_AG4kiQQ |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=NON-VOLATILE+SEMICONDUCTOR+MEMORY+AND+VOLTAGE+TRIMMING+METHOD+FOR+THE+SAME&rft.inventor=FUJIMURA+SUSUMU&rft.date=2014-02-24&rft.externalDBID=A&rft.externalDocID=JP2014035776A |