NAND FLASH MEMORY UNIT, NAND FLASH MEMORY ARRAY, AND METHODS FOR OPERATING THEM

PROBLEM TO BE SOLVED: To reduce a threshold shift of a select transistor caused by holes injected into or drawn out of a trapping layer under a gate of said transistor during erasure, in a NAND flash memory.SOLUTION: A NAND flash memory unit includes: a string 20 of memory cells connected in series;...

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Bibliographic Details
Main Authors LIN WEI, NINA MITIUKHINA, SHIRATA RIICHIRO, KUO TSAI-HAO
Format Patent
LanguageEnglish
Published 15.08.2013
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
INFORMATION STORAGE
PHYSICS
SEMICONDUCTOR DEVICES
STATIC STORES
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Summary:PROBLEM TO BE SOLVED: To reduce a threshold shift of a select transistor caused by holes injected into or drawn out of a trapping layer under a gate of said transistor during erasure, in a NAND flash memory.SOLUTION: A NAND flash memory unit includes: a string 20 of memory cells connected in series; at least one select transistor 22 coupled to both ends of the string; and at least one erase transistor 24 coupled to the at least one select transistor and an S/D region. The select transistor is for selecting the string of memory cells, and the erase transistor is for reducing a threshold shift of the select transistor.
Bibliography:Application Number: JP20120162932