MULTILAYER WIRING BOARD AND MANUFACTURING METHOD OF THE SAME
PROBLEM TO BE SOLVED: To provide a multilayer wiring board which makes cracks less likely to be caused in a resin insulation layer and is excellent in reliability.SOLUTION: A multilayer wiring board includes: a board body; an inner layer wiring pattern 28; a lower layer side resin insulation layer 1...
Saved in:
Main Authors | , |
---|---|
Format | Patent |
Language | English |
Published |
04.04.2013
|
Subjects | |
Online Access | Get full text |
Cover
Loading…
Abstract | PROBLEM TO BE SOLVED: To provide a multilayer wiring board which makes cracks less likely to be caused in a resin insulation layer and is excellent in reliability.SOLUTION: A multilayer wiring board includes: a board body; an inner layer wiring pattern 28; a lower layer side resin insulation layer 16; and an upper layer side resin insulation layer 30. The inner layer wiring pattern 28 extends along the surface direction of the board body. The lower layer side resin insulation layer 16 contacts with the bottom surface 44 side of the inner layer wiring pattern 28. The upper layer side resin insulation layer 30 is located adjacent to the lower layer side resin insulation layer 16 and contacts with an upper surface 43 side of the inner layer wiring pattern 28. The inner layer wiring pattern 28 is buried in both the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30. The largest width part 54 of a cross section surface, when viewed in the lamination direction of the inner layer wiring pattern 28, is disposed at a position between a pattern upper end 51 and a pattern lower end 52. |
---|---|
AbstractList | PROBLEM TO BE SOLVED: To provide a multilayer wiring board which makes cracks less likely to be caused in a resin insulation layer and is excellent in reliability.SOLUTION: A multilayer wiring board includes: a board body; an inner layer wiring pattern 28; a lower layer side resin insulation layer 16; and an upper layer side resin insulation layer 30. The inner layer wiring pattern 28 extends along the surface direction of the board body. The lower layer side resin insulation layer 16 contacts with the bottom surface 44 side of the inner layer wiring pattern 28. The upper layer side resin insulation layer 30 is located adjacent to the lower layer side resin insulation layer 16 and contacts with an upper surface 43 side of the inner layer wiring pattern 28. The inner layer wiring pattern 28 is buried in both the lower layer side resin insulation layer 16 and the upper layer side resin insulation layer 30. The largest width part 54 of a cross section surface, when viewed in the lamination direction of the inner layer wiring pattern 28, is disposed at a position between a pattern upper end 51 and a pattern lower end 52. |
Author | HIGO ICHIEI HIDA TOSHINORI |
Author_xml | – fullname: HIDA TOSHINORI – fullname: HIGO ICHIEI |
BookMark | eNrjYmDJy89L5WSw8Q31CfH0cYx0DVII9wzy9HNXcPJ3DHJRcPRzUfB19At1c3QOCQWL-7qGePi7KPi7KYR4uCoEO_q68jCwpiXmFKfyQmluBiU31xBnD93Ugvz41OKCxOTUvNSSeK8AIwNDYwMzIyNLI0djohQBAF22K48 |
ContentType | Patent |
DBID | EVB |
DatabaseName | esp@cenet |
DatabaseTitleList | |
Database_xml | – sequence: 1 dbid: EVB name: esp@cenet url: http://worldwide.espacenet.com/singleLineSearch?locale=en_EP sourceTypes: Open Access Repository |
DeliveryMethod | fulltext_linktorsrc |
Discipline | Medicine Chemistry Sciences |
ExternalDocumentID | JP2013062292A |
GroupedDBID | EVB |
ID | FETCH-epo_espacenet_JP2013062292A3 |
IEDL.DBID | EVB |
IngestDate | Fri Jul 19 11:40:50 EDT 2024 |
IsOpenAccess | true |
IsPeerReviewed | false |
IsScholarly | false |
Language | English |
LinkModel | DirectLink |
MergedId | FETCHMERGED-epo_espacenet_JP2013062292A3 |
Notes | Application Number: JP20110198192 |
OpenAccessLink | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130404&DB=EPODOC&CC=JP&NR=2013062292A |
ParticipantIDs | epo_espacenet_JP2013062292A |
PublicationCentury | 2000 |
PublicationDate | 20130404 |
PublicationDateYYYYMMDD | 2013-04-04 |
PublicationDate_xml | – month: 04 year: 2013 text: 20130404 day: 04 |
PublicationDecade | 2010 |
PublicationYear | 2013 |
RelatedCompanies | NGK SPARK PLUG CO LTD |
RelatedCompanies_xml | – name: NGK SPARK PLUG CO LTD |
Score | 2.8899682 |
Snippet | PROBLEM TO BE SOLVED: To provide a multilayer wiring board which makes cracks less likely to be caused in a resin insulation layer and is excellent in... |
SourceID | epo |
SourceType | Open Access Repository |
SubjectTerms | CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS |
Title | MULTILAYER WIRING BOARD AND MANUFACTURING METHOD OF THE SAME |
URI | https://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130404&DB=EPODOC&locale=&CC=JP&NR=2013062292A |
hasFullText | 1 |
inHoldings | 1 |
isFullTextHit | |
isPrint | |
link | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dS8Mw8JhT1DedynQqQWRvxZFlbQcOyZqUbqwfzFbn02ibFkTohqv4903jpnvaW7iD43Lh7nLJfQDcG1iQjikMLdcNQyNZL9biuK9roptnJBU9U5hV7bDr6U5ExrPerAYfm1oY1Sf0WzVHlBqVSn0vlb1e_j9iMZVbuXpI3iVo8WSHA9ZeR8fSIBN56Gw44IHPfKttWYNx0Pamvzgd4z6me7Av79FGlf_FX4ZVWcpy26fYJ3AQSHJFeQq1rGjAkbUZvdaAQ3f94y2Xa-VbncGjG03C0YS-8Sl6HVVZDGjo0ylD1GPIpV5kUyuMFNzloeMz5NsodDh6pi4_hzubh5ajSTbmf5uej4MtlrsXUC8WRdYElCe69Pp52k87guBMBphEylPkSdqJBTaTS2jtIHS1E9uCY6ymPVS5KddQLz-_shvpc8vkVsnqB2N3f_c |
link.rule.ids | 230,309,783,888,25578,76884 |
linkProvider | European Patent Office |
linkToHtml | http://utb.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwfR1dS8Mw8JhTnG86FXV-BJG9FUeXtR04JGtautkvZqrzabRNCyJ0w1X8-6Zx0z3tLdzBcblwd7nkPgDudJXjjsF1Jdd0XcFZL1biuK8pvJtnOOU9gxtV7bDna06Ex9PetAYf61oY2Sf0WzZHFBqVCn0vpb1e_D9iUZlbubxP3gVo_mizAW2vomNhkLE4dDocWGFAA7NtmoNx2PYnvzhNVfsq2YFdccc2qkb71suwKktZbPoU-xD2QkGuKI-glhVNaJjr0WtN2PdWP95iuVK-5TE8eJHLRi55sybodVRlMaBhQCYUEZ8ij_iRTUwWSbhnMSegKLARcyz0TDzrBG5ti5mOItiY_W16Ng43WO6eQr2YF9kZoDzRhNfP037a4VjNRICJhTx5nqSdmKtGcg6tLYQutmJvoOEwz525I_-pBQeqnPxQ5alcQr38_MquhP8tk2sptx-L24Ln |
openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Apatent&rft.title=MULTILAYER+WIRING+BOARD+AND+MANUFACTURING+METHOD+OF+THE+SAME&rft.inventor=HIDA+TOSHINORI&rft.inventor=HIGO+ICHIEI&rft.date=2013-04-04&rft.externalDBID=A&rft.externalDocID=JP2013062292A |