APPARATUS, METHOD AND PROGRAM FOR DESIGN OF LAYOUT

• Main Author: KOSUGE YOSHIE
• Format: Patent
• Language: English
• Published: 28.10.2010
• Subjects: BASIC ELECTRIC ELEMENTS; CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; PHYSICS; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a layout design apparatus capable of designing a semiconductor integrated circuit so that a chip size becomes small. SOLUTION: The layout design apparatus includes: a timing analysis unit 103 for performing timing analysis based on a net list and delay information; a...