SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

PROBLEM TO BE SOLVED: To provide a technique improving integration of a semiconductor integrated circuit device. SOLUTION: Wiring 8 positioned in a layer lower than first-layer wiring M1 and consisting of a conductive material film integrated with gate electrodes 7N2, 7P2 of a MISFET for composing a...

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Bibliographic Details
Main Author SHIMIZU YOJI
Format Patent
LanguageEnglish
Published 24.06.2010
Subjects
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Summary:PROBLEM TO BE SOLVED: To provide a technique improving integration of a semiconductor integrated circuit device. SOLUTION: Wiring 8 positioned in a layer lower than first-layer wiring M1 and consisting of a conductive material film integrated with gate electrodes 7N2, 7P2 of a MISFET for composing a 2-in NAND circuit 6 or an inverter circuit 1 is used, without using wiring not less than second-layer wiring, for connecting the 2-input NAND circuit 6 in an upper stage of a cell row and the inverter circuit 1 in a lower stage of a cell row adjacently disposed in a height direction of cells. COPYRIGHT: (C)2010,JPO&INPIT
Bibliography:Application Number: JP20080314818