PHASE ERROR DETECTING CIRCUIT, PHASE LOCKED LOOP CIRCUIT, AND INFORMATION REPRODUCING DEVICE

PROBLEM TO BE SOLVED: To detect a phase error with good accuracy even if an amplification level of a read signal varies in a phase error detection circuit and to stabilize the phase synchronization characteristic of a phase locked loop circuit. SOLUTION: The phase error detection circuit 7 includes...

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Bibliographic Details
Main Author AMADA NOBUTAKA
Format Patent
LanguageEnglish
Published 15.05.2008
Subjects
AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
INFORMATION STORAGE
INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORDCARRIER AND TRANSDUCER
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To detect a phase error with good accuracy even if an amplification level of a read signal varies in a phase error detection circuit and to stabilize the phase synchronization characteristic of a phase locked loop circuit. SOLUTION: The phase error detection circuit 7 includes a computing unit which calculates a ratio Cn (=An/2/Bn) of a sum An and a difference Bn relating to a signal level Xn, Xn-1in continuous two sampling positions (n), (n-1) of the input signal. The calculation result Cn in the sampling position where the polarities of the signal levels Xn, Xn-1 change is outputted as the phase error signal Tn. Furthermore, the calculated value of An is outputted as the error signal Sn of the input signal DC. COPYRIGHT: (C)2008,JPO&INPIT
Bibliography:Application Number: JP20060293480