SEMICONDUCTOR PACKAGING SUBSTRATE, SEMICONDUCTOR PACKAGE USING SAME, AND METHOD OF MANUFACTURING THEM

• Main Authors: TSUBOMATSU YOSHIAKI, INOUE FUMIO, MORIIKE MICHIO
• Format: Patent
• Language: English
• Published: 06.09.2007
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; SEMICONDUCTOR DEVICES

PROBLEM TO BE SOLVED: To provide a compact semiconductor package that can reduce a size, a thickness, and costs conspicuously, can improve density, has superior reliability, such as package crack prevention, and can reduce the number of vent holes or eliminate them. SOLUTION: In the manufacturing method of a semiconductor packaging substrate: a support having an insulating layer 1 and a removable carrier layer 2 is formed at a semiconductor packaging side; an opening 3 is formed in the support at a place, where an external connection terminal 10 is formed; wiring 5 is formed at the side of the insulating layer 1 in the support by bonding metal foil 4 for etching the metal foil 4; and a plurality of sets of a region for packaging the semiconductor chip 6 and a region that is outside the regions, is sealed by a sealing resin 9, and becomes one portion of the semiconductor package are arranged in an array equally for formation. COPYRIGHT: (C)2007,JPO&INPIT