HOUSING OF SEMICONDUCTOR WAFER

PROBLEM TO BE SOLVED: To house a very fragile and delicate wafer in a housing by laminating in multilevel form without breakage. SOLUTION: The semiconductor wafer W is housed in a tray 3 with its both surfaces sandwiched by spacer sheets 2, 2. The tray 3 housing the semiconductor wafer W are stacked...

Full description

Saved in:
Bibliographic Details
Main Authors YANAGAWA TATSUYA, FUYUMURO MASAHIKO
Format Patent
LanguageEnglish
Published 14.07.2005
Edition7
Subjects
ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR
BASIC ELECTRIC ELEMENTS
CONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS,e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES,DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS
CONVEYING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
HANDLING THIN OR FILAMENTARY MATERIAL
PACKAGES
PACKAGING ELEMENTS
PACKING
PERFORMING OPERATIONS
SEMICONDUCTOR DEVICES
STORING
TRANSPORTING
Online AccessGet full text

Cover

More Information
Summary:PROBLEM TO BE SOLVED: To house a very fragile and delicate wafer in a housing by laminating in multilevel form without breakage. SOLUTION: The semiconductor wafer W is housed in a tray 3 with its both surfaces sandwiched by spacer sheets 2, 2. The tray 3 housing the semiconductor wafer W are stacked in not less than two stages and the laminate is housed in a containment vessel through cushions. The cushions are compressed in a covered containment vessel and the compressive force are applied only to the laminate of the tray of each stage. A support 13b of the lower stage tray 3b is fitted within a support 12a of the upper tray 3a in the tray 3 of each stage stacked in not less than 2 stages, the semiconductor wafer W is housed in the housing space between the upper and lower trays 3a, 3b without the compressive force applied. COPYRIGHT: (C)2005,JPO&NCIPI
Bibliography:Application Number: JP20030433319