LEVEL SHIFTER CIRCUIT, METHOD FOR CONTROLLING VOLTAGE LEVEL OF CLOCK SIGNAL, AND INVERTED CLOCK SIGNAL FOR DRIVING GATE LINE OF ASG-THIN FILM TRANSISTOR LIQUID CRYSTAL DISPLAY PANEL

• Main Authors: CHOI CHUL, LEE SAIKYU, HAN BYUNG-HUN
• Format: Patent
• Language: English
• Published: 09.06.2005
• Edition: 7
• Subjects: ADVERTISING; ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION; BASIC ELECTRONIC CIRCUITRY; CALCULATING; COMPUTING; COUNTING; CRYPTOGRAPHY; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING; DISPLAY; EDUCATION; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL ANALOGUE/DIGITAL CONVERTERS; OPTICAL LOGIC ELEMENTS; OPTICS; PHYSICS; PICTORIAL COMMUNICATION, e.g. TELEVISION; PULSE TECHNIQUE; SEALS; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF

PROBLEM TO BE SOLVED: To provide a level shifter circuit and a voltage level control method for controlling the voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin-film transistor liquid crystal display panel. SOLUTION: A level shifter circuit 400 includes a first shifter 419 and a second level shifter 440. The first level shifter controls the voltage level of a clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases or decreases the voltage levels of a clock signal while a precharge clock activating signal is activated. The second level shifter controls the voltage level of an inverted clock signal to swing between a negative external voltage level and a positive external voltage level in response to an inverted clock activating signal, and increases or decrease the voltage levels of an inverted clock signal while an inverted precharge clock activating signal is activated. COPYRIGHT: (C)2005,JPO&NCIPI