INSTRUCTION ROLL BACK PROCESSOR SYSTEM, INSTRUCTION ROLL BACK METHOD, AND INSTRUCTION ROLL BACK PROGRAM

PROBLEM TO BE SOLVED: To provide a high-performance and low-cost instruction roll back processor system having a function which stores instructions in ring-shaped pipeline register PLG groups to rerun during a roll back operation, and reissues the instructions from instruction window buffer IWB duri...

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Bibliographic Details
Main Author TERUYAMA TATSUO
Format Patent
LanguageEnglish
Published 16.09.2004
Edition7
Subjects
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Summary:PROBLEM TO BE SOLVED: To provide a high-performance and low-cost instruction roll back processor system having a function which stores instructions in ring-shaped pipeline register PLG groups to rerun during a roll back operation, and reissues the instructions from instruction window buffer IWB during an instruction re-issuance operation. SOLUTION: The system comprises an IWB2 which stores instructions to be issued and issues the instructions when the instructions can be issued, a multiplexer MUX11 which is connected to the IWB2, a roll back unit 9 comprising PLG13-16 each of which has multiple steps and is connected to the MUX11, a decoder unit 12 which is connected to the roll back unit 9, a control unit 8 which is connected to the decoder unit 12, and a roll back control unit 10 which is connected to the control unit 8 and issues roll back control signals to the MUX11. The system is characterized by connecting output from the roll back control unit 9 to another input of the MUX11. COPYRIGHT: (C)2004,JPO&NCIPI
Bibliography:Application Number: JP20030049933