DOT CLOCK REPRODUCING DEVICE
PROBLEM TO BE SOLVED: To provide a dot clock reproducing device capable of automatically adjusting a dot clock frequency with a high precision. SOLUTION: A dot clock DCK is generated on the basis of a synchronizing signal by a PLL circuit 14, and an inputted video signal is sampled in response to th...
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Main Authors | , |
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Format | Patent |
Language | English |
Published |
08.01.2004
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Edition | 7 |
Subjects | |
Online Access | Get full text |
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Summary: | PROBLEM TO BE SOLVED: To provide a dot clock reproducing device capable of automatically adjusting a dot clock frequency with a high precision. SOLUTION: A dot clock DCK is generated on the basis of a synchronizing signal by a PLL circuit 14, and an inputted video signal is sampled in response to the dot clock DCK to obtain sample values by an A/D converter 11. Sample values are successively received, and a plurality of sample points where sample values are changed like pulses in a one-period width of the dot clock, and absolute values of differences between sample values at adjacent sample points constituting pulse-like change in the one-period width are successively accumulated by an accumulation circuit 24. The phase of the dot clock generated by a dot clock generation circuit is controlled by a control circuit 28 on the basis of a ratio of a minimum value to a maximum value of a plurality of accumulation results obtained at intervals of a prescribed period. As a result, the dot clock is controlled to perform control of high precision. COPYRIGHT: (C)2004,JPO |
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Bibliography: | Application Number: JP20020160842 |