DATA TRANSFER DEVICE

• Main Author: TAKEBE SHIN
• Format: Patent
• Language: English
• Published: 11.10.2002
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC DIGITAL DATA PROCESSING; PHYSICS

PROBLEM TO BE SOLVED: To successively transfer data being output from the memory of a synchronous FIFO to a PCI bus, and also transfer the data without losing even if disabled by the controller of the other party when transferring multiple data to the PCI bus. SOLUTION: When a ready signal #TRDY being output from a second controller (a target controller) is disabled for one clock of a clock signal PCIck, a holding clock enable signal FFCE being enabled corresponding to the one clock is inputted in a data holding means 4. By the data holding means 4, memory data MD are held at the next clock of the clock signal PCIck in which the holding clock enable signal FFCE is enabled. Furthermore, either of the memory data MD or holding data FD are outputted by means of data output control means 5a, 5b, and the next data are transferred to a data bus 3.