DUAL PLL FREQUENCY SYNTHESIZER CIRCUIT

• Main Author: TOYOOKA TAMOTSU
• Format: Patent
• Language: English
• Published: 19.12.2000
• Edition: 7
• Subjects: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES; BASIC ELECTRONIC CIRCUITRY; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRICITY; TRANSMISSION

PROBLEM TO BE SOLVED: To prevent the influence of spurious with a simple constitution without being constrained by the reference signal of a first PLL frequency synthesizer circuit. SOLUTION: In a first PLL frequency synthesizer circuit 17, a first reference frequency-divider 3 generates a first reference signal fs1(=ftcxo/N) obtained by frequency-dividing a reference clock ftcxo by a frequency-division value N(N is a natural number which is 2 or more) according to a frequency-division control signal outputted from a CPU 16, and supplies it to a first phase comparator 4. In a second PLL frequency synthesizer circuit 18, a phase inverting circuit 9 inverts the phase of a reference clock ftcxo supplied from a TCXO2, and generates a phase shift signal ftcxo', and supplies it to a second reference frequency-divider 10.