METHOD AND SYSTEM FOR VERIFYING ERROR OF SHORT CELL ON ATM NETWORK

• Main Authors: KUBOTA HIROMICHI, GOTO MORITAKA
• Format: Patent
• Language: English
• Published: 24.10.2000
• Edition: 7
• Subjects: CALCULATING; COMPUTING; COUNTING; ELECTRIC COMMUNICATION TECHNIQUE; ELECTRIC DIGITAL DATA PROCESSING; ELECTRICITY; PHYSICS; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION

PROBLEM TO BE SOLVED: To improve reliability in waste processing caused by the short cell error of an AAL2 cell in the AAL2 signal processing based on ITU-T recommendation I.363.2. SOLUTION: The length display information of a short cell on the next stage is added to the end of each short cell generated by a base station/relay device 11 excepting the short cells of those at the final stage and the preceding stage to it and of those in which cell spanning occurs, and in the waste processing of cells, an AAL2 cell verifying circuit 12 performs CRC5 by judging the position of each short cell header on the basis of contents in a length display information field inside an OSF and the cell header, performs CRC5 again by judging the position of the short cell header on the next stage by referring to the length display information added at the time of error detection and performs waste processing or transmits that short cell through communication path 13 according to the result.