DISPOSITIVO DI MEMORIA A SEMICONDUTTORE

• Main Author: CHOI YUN-HO
• Format: Patent
• Language: Italian
• Published: 18.07.1992
• Edition: 5
• Subjects: BASIC ELECTRIC ELEMENTS; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR; ELECTRICITY; INFORMATION STORAGE; PHYSICS; SEMICONDUCTOR DEVICES; STATIC STORES

A semiconductor memory device includes an address transition detection circuit for detecting the state transition of address signals and generating a pulse having a predetermined pulse width, a precharge circuit for generating and equalizing a pair of input/output lines in response to the output pulse of the address transition detection circuit, address decoder circuit for decoding the address signals and generating an address selection signal, and a gate circuit connecting the pair of input/output lines to a selected pair of bit lines in response to the address selection signal of the address decoder circuit. In the device, the address decoder circuit has a signal delay characteristic for delaying signals from the state transition of the address signal until the completion of the precharge and equalization of the I/O lines. Accordingly, the access time of the memory address can be operated in high speed by forming the address decoder independent of an ATD pulse, and the circuit can be easily designed and the cost can be saved by eliminating the wiring between the ATD circuit and the address decoder.